1. Field of the Invention
This invention relates to a semiconductor memory device. In particular, the invention relates to an improved semiconductor memory device for controlling the potential difference of respective pairs of row lines in a memory cell array of a static random access memory(SRAM).
2. Description of the Related Art
Various schemes have been adopted to get fast access time of data reading in SRAMs. The chief method which is used at present is to short-circuit a pair of differential input terminals of a sensing amplifier before the address is changed and the column line corresponding to that address is selected and driven. With this method, the speed of data reading is increased by pre-setting the two input potentials of the sensing amplifier to the same level and then speeding up the application of the potential difference to the pair of row lines in accordance with the data read out from the selected memory cell.
FIG. 1 shows a single column of a memory cell array in a conventional SRAM adopting this method, and the corresponding data reading system. The chief signal waveforms during the reading operation are shown in FIG. 2. More particularly, when an address Add is inputted, a static memory cell 82 is selected in accordance with a selection signal WL of the column line 81 corresponding to this address. Data in the form of two complementary signal levels, referred to herein as Q and Q, is stored in memory cell 82. Prior to the complementary level data Q and Q being read out onto the pair of row lines 83 and 83, precharging transistors 84 and 85 and equalizing transistor 86 are turned ON by changing a control signal .phi. to level "1". This control signal .phi. is generated in response to an address transition. The turning ON of these three transistors 84, 85 and 86 short-circuits the pair of row lines 83 and 83, thereby equalizing their potentials. When control signal .phi. is then subsequently changed to level "0", this turns the transistors 84, 85 and 86 OFF so that the data can be read out from this selected memory cell 82. In this process, there is a rapid increase in the potential difference between row lines 83 and 83, which is detected as data by sensing amplifier 87. This detected data is fed to output buffer 88, from which output data Dout is obtained.
As mentioned above, in a conventional SRAM the control signal .phi. is changed to level "1" at a prescribed time after the address Add has changed. Desirably, the cycle of level "1" of this control signal .phi. should be the period until the selected column line has been completely brought up to level "1". The reason for this is that if this control signal .phi. drops to level "0" before the newly selected column line has become level "1", the potentials of the pair of row lines, which were previously made equal by short-circuiting, will return to their original values depending on the read-out data from the previously selected memory cell. If this situation arises, a long time period will be necessary to sufficiently increase the potential across the row lines in response to the read data of the newly selected memory cell.
In contrast, if control signal .phi. is made level "0" after the newly selected column line has been completely brought up to level "1", the sensing amplifier cannot detect the data, since the pair of row lines is short-circuited while control signal .phi. is kept at level "1". In this case, the speed of reading the data is decreased. The period for which control signal .phi. remains at level "1" is therefore vitally important. However, normally this control signal .phi. is formed by comparing the address signal and a signal obtained by delaying this address signal. If, therefore, there is any change in the delay time of the signal due to statistical scatter in the characteristics of the transistors making up the circuit, this will result in statistical scatter of the period for which this control signal .phi. is level "1". Thus it is very difficult to optimize this delay time.